1. Field of the Invention
The invention relates to an output buffer, and more particularly, to an output buffer with high voltage tolerance.
2. Description of the Related Art
Nowadays, in advanced CMOS (Complementary Metal-Oxide-Semiconductor) processes (such as 28 nm processes), the gate oxide breakdown voltage and drain-source punch-through voltage of MOS transistors are lower as compared with previous processes (such as 40 nm processes). High voltage devices cannot be manufactured by the advanced CMOS processes. For example, 3.3V devices may not be manufactured by the 28 nm processes. However, some peripheral components or other ICs not manufactured by advanced processes may still operate in high voltages such as 3.3V. The signals generated in the peripheral components or other ICs may have high voltage levels. When the MOS transistors fabricated with the 28 nm processes receive these signals, the MOS transistors may be damaged by the high voltage levels. For example, high voltage differences between the gate and source/drain of the MOS transistors (i.e. large Vgs or Vgd) may result in gate oxide breakdown, and high voltage differences between the source and drain of the MOS transistors (i.e. large Vds) may result in punch-through. Therefore, it is critical to prevent the Vgs, Vgd, and Vds of the MOS transistors from exceeding a certain limit. For the case of MOS transistors fabricated with the 28 nm processes, the Vgs, Vgd, and Vds should remain below about 1.8V to prevent such damages.